1. Technical Field
The present invention relates to semiconductor memory apparatuses, and more particularly, to data input/output of a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus may perform data input/output operations by receiving data through pads from outside the semiconductor memory apparatus and storing the data in memory banks and by outputting the data stored in the memory banks through the pads. These operations are called read/write operations of the semiconductor memory apparatus. The data may be transmitted between the pads and the memory banks through data input/output lines.
FIG. 1 is a diagram schematically illustrating a configuration of a conventional semiconductor memory apparatus. The conventional semiconductor memory apparatus 10 shown in FIG. 1 includes first through eighth memory banks Bank0 through Bank7, a plurality of data input/output lines GIO_0<0:15> through GIO_7<0:15>, and data input/output units 11, 12, and 13. The data input/output units 11, 12, and 13 are connected to pads (not shown). The data input/output units 11, 12, and 13 and the first through eighth memory banks Bank0 through Bank7 may communicate with each other through the data input/output lines GIO_0<0:15> through GIO_7<0:15>. A plurality of the data input/output units 11, 12, and 13 are provided for each memory bank. FIG. 1 illustrates only data alignment circuits Din associated with data input (a write operation) and only pipe latch circuits PIPE associated with data output (a read operation) of the data input/output units 11, 12, and 13 to simplify the description.
During the write operation, the semiconductor memory apparatus 10 may input serial data from outside the semiconductor memory apparatus 10 through the pads, convert the serial data into parallel data through the data alignment circuits Din, which is a part of the data input/output units 11, 12, and 13, transmit the parallel data to corresponding memory banks through the data input/output lines GIO_0<0:15> through GIO_7<0:15>, and store the transmitted data in the corresponding memory banks. During the read operation, the semiconductor memory apparatus 10 may transmit the data stored in the corresponding memory banks to the pipe latch circuits PIPE, which isa part of the data input/output units 11, 12, and 13, through the data input/output lines GIO_0<0:15> through GIO_7<0:15>. The pipe latch circuits PIPE may convert the data transmitted in parallel into serial data, and output the converted data externally through the pads.
As described above, during the write operations and the read operations, the data input/output lines GIO_0<0:15> through GIO_7<0:15> function as data transmission paths. The data input/output lines GIO_0<0:15> through GIO_7<0:15> are disposed in a peripheral region between the memory banks Bank0 through Bank7. As a processing capacity of a semiconductor memory apparatus increases, the number of the data input/output lines GIO_0<0:15> through GIO_7<0:15> increases. For example, as shown in FIG. 1, in order for the semiconductor memory apparatus 10 to process 16-bit data at a time while performing eight read or write operations continuously, a total of 128 data input/output lines GIO_0<0:15> through GIO_7<0:15> are needed. Therefore, if the plurality of data input/output lines GIO_0<0:15> through GIO_7<0:15> are disposed in the peripheral region of a limited area as described above, it may be difficult to secure a layout margin of the semiconductor memory apparatus.